1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various embodiments of an improved metal gate structure for semiconductor devices, such as transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent an important type of circuit element that substantially determines performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS (metal-oxide-semiconductor) technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, since the speed of creating the channel, which depends in part on the conductivity of the gate electrode, and the channel resistivity substantially determine the characteristics of the transistor, reducing channel length (or scaling), and associated therewith the reduction of channel resistivity and the increase of gate resistivity, are dominant design efforts used to increase the operating speed of the integrated circuits.
For many early device technology generations, the gate structures of most transistor devices were made of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode structures comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate electrode structures or stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over transistors that employed traditional gate structures comprised of the previously described silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in HK/MG gate electrode structures. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
FIG. 1 depicts one illustrative prior art transistor 10 with an HK/MG gate structure 22. As shown in FIG. 1, the process includes the formation of a basic transistor structure 10 above a semiconducting substrate 11 in an active area defined by a shallow trench isolation structure 13. At the point of fabrication depicted in FIG. 1, the gate structure 22 of the device 10 includes a silicon dioxide gate insulation layer 12 having a thickness of about 1 nm, a layer of hafnium oxide 14 having a thickness of about 1.7 nm, a first layer of titanium nitride 16 having a thickness of about 1.5 nm, a layer of aluminum 18 having a thickness of about 0.2 nm, a second layer of titanium nitride 20 having a thickness of about 0.5 nm and a layer of polysilicon 21 having a thickness of about 50-65 nm. Also depicted in FIG. 1 is an illustrative protective gate cap layer 23 (e.g., silicon nitride), illustrative sidewall spacers 24 (e.g., silicon nitride), a layer of insulating material 26 (e.g., silicon dioxide) and source/drain regions 15 formed in the substrate 11.
The various components and structures of the device 10 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sidewall spacers 24 may be comprised of silicon nitride and the layer of insulating material 26 may be comprised of silicon dioxide. The source/drain regions 15 may be comprised of implanted dopant materials (N-type dopants for NFET devices and P-type dopant for PFET devices) that are implanted into the substrate using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 10 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high-performance PFET transistors. In some cases, layers of metal other than the titanium nitride layers may be employed in such devices and other high-k insulation materials may be used in the device 10 instead of the depicted layer of hafnium oxide 14.
The device depicted in FIG. 1 may be formed using traditional gate-first manufacturing techniques. For example, in a CMOS product, after the N and P wells are formed in the substrate, the channel silicon/germanium layer for the PFET devices may be formed, followed by the formation of the gate insulation layer 12. Then, the high-k insulation layer 14, e.g., hafnium oxide, is deposited on the gate insulation layer 12 for both the PFET and NFET devices. Thereafter, work function adjusting metals (not shown), such as lanthanum and aluminum, are deposited for the NFET and PFET devices (with appropriate masking layers in place). A work function anneal process is then performed to drive metal from the work function metals into the high-k insulation layer 14. All work function adjusting metal materials may then be removed and the final metal layer(s) for the device, e.g., layers 16, 18 and 20, may be deposited on both the NFET and PFET devices. Thereafter, the polysilicon layer 21 may then be deposited over the final metal layer(s). The gate cap layer 23, e.g., silicon dioxide, may then be deposited above the layer of polysilicon 21. Thereafter, the various layers of material are patterned into the final gate structure for the device using known etching and photolithography techniques.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.